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TOELY
OTCInformation Technology · Semiconductors & Semiconductor Equipment
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Structural: one of five WFE oligopolists ($ASML lithography, $AMAT/$LRCX/$KLAC/TEL everything else). Coater/developer is a near-monopoly (~90% share) - every EUV scanner ships with a TEL track, making TOELY a structural co-beneficiary of every $ASML EUV/High-NA placement.
Also top-3 in etch (high-aspect-ratio for 3D NAND, GAA logic), deposition (ALD, CVD), and the only non-U.S. supplier with full toolset breadth.
(1) HBM3E/HBM4 ramp lifts DRAM etch + deposition intensity 2-3x per wafer. (2) GAA transistor transition at N2/A14 ($TSM, $INTC 18A, Samsung) doubles etch + ALD steps. (3) Sustained China WFE spend (mature nodes, BOE/CXMT/YMTC) - TEL less U.S.-export-restricted than $AMAT/$LRCX.
(4) High-NA EUV ramp 2026-2028 = mandatory new track tools. (5) Yen tailwind for USD-revenue Japanese exporters.
(1) WFE is cyclical - memory capex can collapse 40%+ peak-to-trough. (2) Customer concentration: top-3 ($TSM, Samsung, SK hynix) = ~50% of revenue. (3) Geopolitical: Japan aligned with U.S. export controls - China revenue (~40%) is the bear-case overhang.
(4) ASML High-NA delays push out coater/developer attach. (5) ADR liquidity is thin vs Tokyo 8035.T listing.
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Auto-computed retracement of the trailing 52w low-high leg. Recomputed on each refresh; not a curated level.
Auto-computed retracement of the trailing 52w low-high leg. Recomputed on each refresh; not a curated level.